A semiconductor integrated circuit (“IC”) is generally susceptible to an electrostatic discharge (“ESD”) event, which may damage or destroy the IC. An ESD event refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration during which a large amount of current is provided to the IC. The high current may be built-up from a variety of sources, such as the human body.
Advanced MOSFET transistors, such as those manufactured using sub-quarter-micron processes, have traditionally required certain processes such as silicide processes, lightly-doped drain (LDD) structures, and thin gate dielectric layers. As a result, the advanced MOSFET transistors are particularly susceptible to an ESD event.
Conventional ESD protection devices are implemented using bipolar junction transistors (“BJTs”), gate grounded NMOS (“GGNMOS”) transistors, silicon controlled rectifiers (“SCR”), and silicon junction diodes, to name a few examples. Conventional NMOS devices have a threshold voltage of about 0.6V adjustable by changing the concentration of the p-type implant in the channel regions. These devices disadvantageously have slow turn-on speed and therefore poor ESD robustness.
An example of a conventional ESD protection device in input/output (I/O) pad design is shown in FIGS. 1 and 2, reproduction of FIGS. 1B and 2, respectively, of U.S. Pat. No. 6,256,184 to Gauthier, entitled “Method and Apparatus for Providing Electrostatic Discharge Protection.” Gauthier describes an ESD protection structure that includes low threshold and zero threshold FETs to conduct transient ESD currents during an ESD event. Referring to FIG. 1, an NMOS 115 for ESD protection device has a low threshold voltage, and, during normal operation, is required to connect to a negative voltage source 201 at the gate to turn off channel current. Referring to FIG. 2, an ESD protection circuit 101 comprises a source diode 203 to minimize leakage current during normal IC operation.
A conventional NMOS device is generally formed in a p-well, and is manufactured by first providing a substrate and forming shallow trench isolations (“STIs”) or local oxidation silicon (“LOCOS”). The steps of p-well implantation, anti-punchthrough implantation, and channel implantation then follow. In general, the p-well has the largest implant depth and the lowest doped concentration, and the channel region has the smallest implant depth and the highest doped concentration. The steps of n-well implantation, anti-punchthrough implantation, and channel implantation follow then. A gate oxide layer is then formed over the substrate, and a gate is formed over the gate oxide layer. Sidewall spacers are formed contiguous with the gate. Finally, source and drain regions are formed to finish the fabrication of the NMOS in a p-well.